1. Field of the Invention
The present invention relates to a technique for verifying and inspecting a designed digital circuit, and more particularly to an input/output probing apparatus which is capable of implementing a designed digital circuit as a programmable chip or as an order-built type semiconductor chip actually by hardware and capable of quickly verifying and inspecting it on an emulation basis, and a method using the same. Further, the present invention relates to a mixed emulation/simulation method which is capable of implementing a designed digital circuit as a programmable chip or as an ASIC semiconductor chip actually by hardware, capable of automatically switching from emulation to simulation executed by means of a simulator on a computer during emulating process, or reversely, capable of automatically switching from simulation executed on the computer by the simulator to emulation, thereby performing emulation and simulation in turn more than one time for verification and a mixed emulation/simulation verifying apparatus therefor.
2. Description of the Related Art
Recently, as a design for an integrated circuit and a semiconductor process technique are being rapidly developed, a design of a digital circuit tends to be enlarged and its construction becomes complicate. Accordingly, as competition in the market turns keen more and more, a method for verifying a designed circuit quickly and effectively is sought to meet the necessity.
Up to now, generally, a simulator, an approach based on software, has been employed to verify a designed digital circuit. Thanks to its advantage of using various delay models for a circuit, the simulation-based verifying method using the simulator allows a timing verification as well as a functional verification, and above all, it provides a perfect visibility for every signal line existing in a circuit during debugging.
However, as for the simulator, since a software code consisting of sequential instruction sequences, which is obtained by modeling the design verification circuit by software, is to be sequentially performed on computer, time for verification is taken for a long time, with a limitation that it fails to be integrated with a peripheral hardware environment for In-Circuit Emulation (referred to as an ICE, hereinafter).
Moreover, referring to the verification through simulation, since performance of a computer dependent on a simulation software and a single processor fails to come up with the complexity of a digital circuit of tens of thousands of gates which are rapidly increased, recently, it incurs an extremely long time to perform a simulation for a general design verification.
Comparatively, a hardware emulation based design verification method, that actually implements a designed circuit as a chip to use it, is advantageous in that since the digital circuit is verified while being parallely operated, design verification can be possibly carried out at a million time speed at the maximum compared to that of the simulation, and ICE environment is possibly constructed with respect to a peripheral hardware environment for integrated verification.
However, the emulation is not good for debugging compared to the simulation. The reason for this is that the visibility showing logic values of numerous signal lines existing in the circuit implemented with programmable chips or ASIC chips is exorbitantly degraded compared to simulation.
As a core device for emulation-based design verification, reusable field programmable devices (referred to as xe2x80x98RFPDxe2x80x99, hereinafter), that is, programmable chips, are employed. The RFPD includes a field programmable gate array and a complex programmable logic device. These days, with development of a semiconductor technique, the RFPD is highly integrated, making it possible to use a single RFPD or a very few RFPD for complex digital circuits and prototype it.
Unlike the implementation of a circuit using the ASIC chip, in case that a circuit is implemented by using the RFPD, it is advantageous in that it can be carried out in the field at a low cost, and time and expense are considerably reduced to correct a bug as being found.
The feature of the present invention also can be applied to a case of using an ASIC chip using a technique such as a standard cell or to a gate array in the same manner as well as the case of using the RFPD for implementation of the design verification circuit, but in the description of the present invention, using of the RFPD is taken for explanation""s convenience.
As mentioned above, though prototyping can be economically performed owing to the development in the highly integrated semiconductor technique, since the numerous signal lines on the digital circuit, the target for design verification in prototyping, mostly exist inside the RFPD, it is difficult to probe the signal lines, degrading visibility for debugging. This problem would be more serious in the future when more highly integrated RFPD is expected to be used.
In order to solve the problem, a method is required for performing an effective and rapid probing even in the case that the signal lines of the circuit exist inside the chip, so that a circuit subjected to design verification as being implemented in the RFPD can be effectively and rapidly debugged.
Besides, in order to maximize the efficiency for design verification of a digital circuit, a method of mixedly using emulation and simulation appropriately in turn during design verifying process is required.
That is, a high speed function verification is carried out to the point of time when and in a specific situation where a very fine identification is required on the emulation basis for design verification. Thereafter, the verifying method is automatically switched from an emulation basis to a simulation basis to perform a functional verification or a timing verification with a 100%-perfect visibility for the target circuit of verification.
In this respect, switching between emulation and simulation is repeated more than one time, as necessary, to thereby maximize efficiency of the verification.
However, to date, in case that a hardware board (referred to as xe2x80x98arbitrary prototyping boardxe2x80x99, hereinafter) on which a digital circuit is implemented with the RFPD, the programmable chip, or with a general ASIC semiconductor chip, is subjected to a design verification on the emulation basis, no input/output probing apparatus using an open architecture that can perform debugging rapidly and effectively even for a hardware board, not limiting to a specific hardware board, and no input/output probing method has been presented.
And, a general tendency shows that designers design a digital circuit by using a gated clock or a locally generated clock, rather than designing a fully synchronous circuit, to reduce a power consumption or due to various reasons.
However, such asynchronous factors make input/output probing for a circuit, especially, an input probing, very difficult. In addition, no input/output probing method has been proposed to cope with such a general situation.
Moreover, there has not been proposed any method and apparatus for mixedly using emulation and simulation for verification to thereby remove the shortcomings of the emulation-based verification method, in a manner of employing the hardware board on which an arbitrary ASIC semiconductor is mounted that implements a circuit subjected to a design verification including the asynchronous factors and an arbitrary simulator.
Especially, in case where simulation is first performed and emulation is subsequently performed, before emulation starts, memory devices and memories which exist in a circuit implemented in the RFPD that performs emulation are to have the same logic values as the logic values at the current time point of the memory devices (flipflops or latches) and the memories (RAM or ROM) of a design verification target circuit obtained by simulation.
However, in preparation for an asychronous situation in which a gated clock and a locally generated clock signal are applied to the clock input of the memory devices existing in the design verification target circuit, no method has been proposed to freely replace the logic values of memory devices existing in the circuit implemented in the RFPD with the specific logic values obtained by the result of simulation.
Furthermore, thanks to the recent development of the Internet technology, a general tendency is that a designer, a software for a design, a simulator, a hardware board for emulation, a server computer are dispersed and connected through network, rather than being collectively positioned in a place.
With such an environment in which the simulator and the hardware board are separately positioned at a distance, no method has been proposed to perform emulation and simulation in turn at a high speed in a time-shared system for a single design verification target circuit through a local area network or a remote area network.
In addition, the above described technique may be applied not only to a design verifying stage of a circuit but also to a testing stage after the circuit is completely fabricated.
A scan technique is one of the widely used technique to inspect the circuit. However, the scan fails to provide any controllable method for the memory devices using the gated clock or the locally generated clock as stated above.
The input/output probing method in accordance with the present invention basically provides a perfect controllability and an observability for any memory devices existing in a circuit, which, thus, is superior to the scan method in the aspect of circuit inspecting.
U.S. Pat. No. 5,937,179 filed by Texas Instrument (TI) discloses a method for performing emulation and simulation in turn. But it employs the above mentioned scan chain, that is, a general technique for circuit inspecting, which is not able to control a circuit if the circuit would include a memory device that would use the gated clock or the locally generated clock.
That is, it has problems that the mixed emulation/simulation is not available to circuits having an asynchronous factor, and it is designed to be adopted only for the completely synchronous circuit in which the same clocks are applied to the every memory device existing therein. Also, since it doesn""t not have an open architecture, it is not possible to be applied to a hardware board.
Therefore, an object of the present invention is to provide a rapid input/output probing apparatus and input/output probing method using the same which are capable of enabling an input/output probing system controller to add a supplementary circuit to a design verification or inspection target circuit to thereby automatically generate an extended circuit suitable for input/output probing so as to be implemented in a semiconductor chip, thereby performing an effective design verification or inspection for a digital circuit.
Another object of the present invention is to provide an input/output probing method for mixedly performing emulation and simulation to perform input/output probing even for any prototyping board by means of an input/output probing apparatus, thereby rapidly and effectively debugging.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided an input/output probing apparatus including an input/output probing system controller and an input/output probing interface module.
The input/output probing system controller of the present invention includes an input/output probing system software, and the input/output probing interface module may include an interface module and an interface cable.
The input/output probing system controller is executed in a server computer, and the server computer may includes a simulator or may be connected with a different computer having a simulator through a remote local area network.
The input/output interface module serves to connected the server computer having the input/output probing system controller with a prototyping board including at least one semiconductor chip (i.e., FPGA) for implementing a designed digital circuit.
Another primary function of the input/output probing interface module is to generate at least one system clock and probing clock required for input/output probing, an operating mode control signal, a probing mode control signal or a probing memory reading/writing signal under the control of the input/output probing system controller and to supply them to the prototyping board as necessary, thereby controlling performing and stopping of the prototyping board.
For this purpose, the input/output probing interface module includes a FPGA or CPLD, microprocessor or a microcontroller, or a special ASIC chip.